Referring initially to FIG. 1, it is typical in a mainframe-computer/server (hereinafter “mainframe”) environment for a system 10 to include a mainframe 12 having at least one central processing unit (CPU) 14 wherein an input/output processor (IOP) 16 is also provided so that input/output processing is offloaded from the CPU 14 to the IOP 16. In such arrangements, the IOP 16 will obtain data from some source such as a local area network (LAN) 18 and send the data to the CPU 14 for delivery to software programs, as appropriate. In this situation, the IOP 16 is referred to as the sender and the CPU 14 is referred to as the receiver. Similarly, once the data has been processed, the CPU 14 will obtain data from the software programs and send the data to the IOP 16 for delivery to the LAN 18. In this situation, the CPU 14 is referred to as the sender and the IOP 16 is referred to as the receiver. In both situations, data obtained by the sender is stored prior to being sent in a plurality of buffers which typically reside in a memory 20 wherein both the CPU 14 and IOP 16 have read/write access.
Referring now to FIG. 2, the basic flow of data in a system 10 as shown in FIG. 1, is that data is placed in a current buffer (i.e. the buffer to be or being filled) by a sender 204 of data and once the buffer is full, the buffer is released by the sender 204 of data to a receiver 206 of data via some queuing or messaging protocol. The receiver 206 then extracts the data and the now empty buffer is released back to the sender 204, again via some queuing or messaging protocol.
The efficiency with which data is exchanged between a sender and receiver is impacted by a number of factors. For example, where a CPU is a receiver, the CPU is a factor in that where a CPU is slow in processing data, it is therefore slow in returning empty buffers. This may result in a lack of empty buffers for a sender (in this case an IOP) causing the sender to delay sending data until an empty buffer is returned by a receiver. The efficiency of data exchange is also impacted by the manner in which a sender sends data to a receiver. That is, when a sender has at least one empty buffer available, it may send a piece of data (e.g. an Internet Protocol (IP) packet) as soon as the sender obtains the packet. However, this is very inefficient because the operation of sending data between a sender and receiver is fairly expensive in terms of the number of processor cycles required. It is therefore preferable to send a plurality of data packets at one time. In this situation, however, systems are typically configured wherein a sender releases buffers to a receiver once the buffers are full. Additionally, some type of time limit is typically used to control the release of partially full buffers after a predetermined time period.
The use of time limits, however, has disadvantages in that they cause inefficiencies regardless of the duration of the time limit that is used. For example, the longer the time limit, the greater the degradation in performance of transaction based protocols where an approximately equal number of packets are traveling in both directions and are preferably exchanged as fast as possible. Conversely, the shorter the time limit, the greater the degradation in performance of streaming protocols wherein large quantities of data packets are sent in a single direction and are preferably exchanged in the largest quantity possible.
It would therefore be desirable to provide a method for exchanging data between a CPU and an IOP that works equally well for transaction based protocols and streaming protocols wherein a sender determines when to release partially full buffers to a receiver.